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? freescale semiconductor, inc., 2005, 2006. all rights reserved. freescale semiconductor technical data freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. document number: mc13202 rev. 0.0, 03/2006 mc13202/203 package information plastic package case 1311-03 ordering information device device marking package mc13202 13202 qfn-32 MC13203 13203 qfn-32 1 introduction the mc13202 and MC13203 are short range, low power, 2.4 ghz industrial, scientific, and medical (ism) band transceivers. the mc13202/MC13203 contain a complete 802.15.4 physical layer (phy) modem designed for the ieee ? 802.15.4 wireless standard which supports peer-to-peer, star, and mesh networking. the mc13202 includes the 802.15.4 phy/mac for use with the hcs08 family of mcus. the MC13203 also includes the 802.15.4 phy/mac plus the zigbee protocol stack for use with the hcs08 family of mcus. with the exception of the add ition of the zigbee protocol stack, the MC13203 functionali ty is the same as the mc13202. when combined with an a ppropriate microcontroller (mcu), the mc13202/MC13203 provides a cost-effective solution for short-range data links and networks. interface with the mcu is accomplished using a four wire serial peripher al interface (spi) connection and an interrupt request outpu t which allows for the use of a variety of processors. the software and processor mc13202/203 2.4 ghz low power transceiver for the ieee ? 802.15.4 standard contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 block diagrams . . . . . . . . . . . . . . . . . . . . . . . 4 4 data transfer modes . . . . . . . . . . . . . . . . . . . 6 5 electrical characteristics . . . . . . . . . . . . . . . 8 6 functional description . . . . . . . . . . . . . . . . 11 7 pin connections . . . . . . . . . . . . . . . . . . . . . . 14 8 crystal oscillator reference frequency . . 18 9 transceiver rf configurations and external connections . . . . . . . . . . . . . . . . . 21 10packaging information . . . . . . . . . . . . . . . . 28
mc13202/203 technical data, rev. 0.0 2 freescale semiconductor can be scaled to fit applications ranging from simple point-to-point systems, through complete zigbee? networking. applications include, but are not limited to, the following: ? residential and commercial automation ? lighting control ? security ? access control ? heating, ventilation, air-conditioning (hvac) ? automated meter reading (amr) ? industrial control ? asset tracking and monitoring ? homeland security ? process management ? environmental mon itoring and control ?hvac ? automated meter reading ? health care ? patient monitoring ? fitness monitoring the transceiver includes a low noise amplifier, 1.0 mw power amplifiers (pa), onboard rf transmit/receive (t/r) switch for single port use, pll with internal voltage cont rolled oscillator (vco), on-board power supply regulation, and full spread-s pectrum encoding and dec oding. the device supports 250 kbps offset-quadrature phas e shift keying (o-qpsk) data in 2.0 mhz channels with 5.0 mhz channel spacing per the ieee 802.15.4 specifica tion. the spi port and interrupt request output are used for receive (rx) and transm it (tx) data transfer and control. 2features ? recommended power supply range: 2.0 to 3.4 v ? fully compliant ieee 802.15.4 tran sceiver supports 250 kbps o-qpsk data in 5.0 mhz channels and full spread-spectrum encode and decode ? operates on one of 16 selectable channels in the 2.4 ghz band ? -1 to 0 dbm nominal output power, program mable from -27 dbm to +3 dbm typical ? receive sensitivity of <-92 dbm (t ypical) at 1% per, 20-byte packet , much better than the ieee 802.15.4 specification of -85 dbm ? integrated transm it/receive switch ? dual pa output pairs which can be programmed fo r full differential single port or dual port operation that supports an external lna and/or pa ? three power down modes for increased battery life
mc13202/203 technical data, rev. 0.0 freescale semiconductor 3 ?< 1 a off current ? 1.0 a typical hibernate current ? 35 a typical doze current (no clko) ? programmable frequency clock output (clko) for use by mcu ? onboard trim capability for 16 mhz crystal refere nce oscillator eliminates need for external variable capacitors and allows for automated production fre quency calibration ? four internal timer comparators availa ble to supplement mcu timer resources ? supports both packet mode and streaming mode data transfer ? buffered transmit and receiv e data packets for simplified use with low cost mcus ? seven gpio to supplement mcu gpio ? operating temperature range: -40 c to 85 c ? small form factor qfn-32 package ? meets moisture sensitivity level (msl) 3 ? 260 c peak reflow temperature ? meets lead-free requirements 2.1 software features freescale provides a wide range of software functionality to co mplement the mc13202/203 hardware. there are three levels of application solutions: 1. simple proprietary wireless connectivity. 2. user networks built on th e ieee 802.15.4 mac standard. 3. zigbee-compliant network stack. 2.1.1 simple mac (smac) ? small memory footprint (about 3 kbytes typical) ? supports point-to-point and st ar network configurations ? proprietary networks ? source code and applicat ion examples provided 2.1.2 ieee 802.15.4-compliant mac ? supports star, mesh and cluster tree topologies ? supports beaconed networks ? supports gts for low latency ? multiple power saving mode s (idle doze, hibernate) 2.1.3 zigbee-compliant network stack ? supports zigbee 1.0 specification
mc13202/203 technical data, rev. 0.0 4 freescale semiconductor ? supports star, mesh and tree networks ? advanced encryption standa rd (aes) 128-bit security 3 block diagrams figure 1 shows a simplified block diagram of the mc13202/MC13203 which is an ieee standard 802.15.4 compatible transceiver that provides the functions required in th e physical layer (phy) specification. figure 2 shows the basic system block di agram for the mc13202/MC13203 in an application. interface with the transceiver is accomplished through a 4-wire spi port and interrupt request line. the media access control (mac), drivers, and network and applicat ion software (as required) reside on the host processor. the hos t can vary from a simple 8-bit device up to a sophi sticated 32-bit processor depending on appli cation requirements. figure 1. 802.15.4 modem simplified block diagram phase shift modulator rst gpio1 gpio2 gpio3 gpio4 xtal2 xtal1 rfin_m (pao_m) pao_p pao_m mosi miso spiclk rxtxen ce attn gpio5 gpio6 gpio7 receive packet ram transmit packet ram 1 transmit ram arbiter receiv e ram arbiter pa vco crystal oscillator sy mbol generation fcs generation header generation mux sequence manager (control logic) vddlo2 4 256 mhz 2.45 ghz lna 1st if mix er if = 65 mhz 2nd if mix er if = 1 mhz pma dec imation filter matched filter baseband mixer dc d correlator symbol synch & det cca packet processor irq arbiter 24 bit ev ent timer irq 16 mhz agc analog regulator vbatt digital regulator l digital regulator h pow er-up control logic crystal regulator vco regulator vddint programmable prescaler clko 4 programmable timer comparators sy nthesizer vddd vddvco serial peripheral interface (spi) vdda vddlo1 transmit packet ram 2 t / r rfin_p (pao_p) ct_bias
mc13202/203 technical data, rev. 0.0 freescale semiconductor 5 figure 2. system level block diagram 4 data transfer modes the mc13202/MC13203 has two data transfer modes: 1. packet mode ? data is buffered in on-chip ram 2. streaming mode ? data is processed word-by-word the freescale 802.15.4 mac software only supports the streaming mode of data transfer. for proprietary applications, packet mode can be used to conserve mcu resources. 4.1 packet structure figure 3 shows the packet structure of the mc13202/MC13203. payloads of up to 125 bytes are supported. the mc13202/MC13203 adds a four-byte preamble, a one-byte start of frame delimiter (sfd), and a one-byte frame length indicator (fl i) before the data. a frame check sequence (fcs) is calculated and appended to the end of the data. figure 3. mc13202/MC13203 packet structure 4.2 receive path description in the receive signal path, the rf input is converted to low if in-phase and qu adrature (i & q) signals through two down-conversion stages. a clear channel assessment (cca ) can be performed based upon analog receiver mc13202/MC13203 frequency generation analog transmitter voltage regulators pow er up management control logic buffer ram digital transceiver spi and gpio microcontroller spi rom (flash) ram cpu a/d timer application irq arbiter ram arbiter timer network mac phy driv er preamble sfd fli payload data fcs 4 bytes 1 byte 1 byte 125 bytes maximum 2 bytes
mc13202/203 technical data, rev. 0.0 6 freescale semiconductor the baseband energy integrated over a specific time in terval. the digital backe nd performs differential chip detection (dcd), the correlator ?de-spreads? the direct sequence spread spectrum (dsss) offset qpsk (o-qpsk) signal, determines the sy mbols and packets, and detects the data. the preamble, sfd, and fli are parsed and used to de tect the payload data and fcs which are stored in ram. a two-byte fcs is calculated on the received data and compared to the fcs value appended to the transmitted data, which generates a cyclical redundancy check (crc) result. link quality is measured over a 64 s period after the packet preamble and stored in ram. if the mc13202/MC13203 is in packet mode, the data is processed as an entire packet. the mcu is notified that an entire packet ha s been received via an interrupt. if the mc13202/MC13203 is in streaming mode, the mc u is notified by an interrupt on a word-by-word basis. figure 4 shows cca reported power level ve rsus input power. note that cca reported powe r saturates at about -57 dbm input power which is well above ieee 802.15.4 standard requirements. figure 5 shows energy detection/lq i reported level versus input power. note for both graphs, the required ieee 802.15.4 standard accuracy and range limits are shown. a 3.5 dbm offset has been programmed into the cca reporting level to center the leve l over temperature in the graphs. figure 4. reported power level versus input power in cca mode -100 -90 -80 -70 -60 -50 -90 -80 -70 -60 -50 input pow er (dbm) reported power level (dbm) 802.15.4 accuracy and range requirements
mc13202/203 technical data, rev. 0.0 freescale semiconductor 7 figure 5. reported power level versus input power for energy detect or link quality indicator 4.3 transmit path description for the transmit path, the tx data th at was previously stored in ram is retrieved (packet mode) or the tx data is clocked in via the spi (s tream mode), formed into packets per the 802.15.4 phy, spread, and then up-converted to the transmit frequency. if the mc13202/MC13203 is in packet mode, data is pr ocessed as an entire pa cket. the data are first loaded into the tx buffer. the mcu then reque sts that the mc13202/MC13203 transmit the data. the mcu is notified via an interrupt when the w hole packet has successful ly been transmitted. in streaming mode, the data is fed to the mc13202/ MC13203 on a word-by-word basis with an interrupt serving as a notificati on that the mc13202/MC13203 is ready for more data. this continues until the whole packet is transmitted. -85 -75 -65 -55 -45 -35 -25 -15 -85 -75 -65 -55 -45 -35 -25 -15 inp ut po w e r le ve l ( dbm) reported power level (dbm) 802.15.4 accuracy and range requirements
mc13202/203 technical data, rev. 0.0 8 freescale semiconductor 5 electrical characteristics 5.1 maximum ratings 5.2 recommended oper ating conditions table 1. maximum ratings rating symbol value unit power supply voltage v batt, v ddint 3.6 vdc rf input power p max 10 dbm junction temperature t j 125 c storage temperature range t stg -55 to 125 c note: maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to t he limits in the electrical characteristics or recommended operating conditions tables. note: meets human body model (hbm) = 2 kv. rf input/output pins have no esd protection. table 2. recommended operating conditions characteristic symbol min typ max unit power supply voltage (v batt = v ddint )v batt, v ddint 2.0 2.7 3.4 vdc input frequency f in 2.405 - 2.480 ghz ambient temperature range t a -40 25 85 c logic input voltage low v il 0-30% v ddint v logic input voltage high v ih 70% v ddint -v ddint v spi clock rate f spi --8.0mhz rf input power p max --10dbm crystal reference oscillator frequency (40 ppm over operating conditions to meet the 802.15.4 standard.) f ref 16 mhz only
mc13202/203 technical data, rev. 0.0 freescale semiconductor 9 5.3 dc electrical characteristics 5.4 ac electrical characteristics table 3. dc electrical characteristics (v batt , v ddint = 2.7 v, t a = 25 c, unless otherwise noted) characteristic symbol min typ max unit power supply current (v batt + v ddint ) off hibernate doze (no clko) idle transmit mode receive mode i leakage i cch i ccd i cci i cct i ccr - - - - - - 0.2 1.0 35 500 30 37 1.0 6.0 102 800 35 42 a a a a ma ma input current (v in = 0 v or v ddint ) (all digital inputs) i in --1 a input low voltage (all digital inputs) v il 0-30% v ddint v input high voltage (all digital inputs) v ih 70% v ddint -v ddint v output high voltage (i oh = -1 ma) (all digital outputs) v oh 80% v ddint -v ddint v output low voltage (i ol = 1 ma) (all digital outputs) v ol 0-20% v ddint v table 4. receiver ac electrical characteristics (v batt , v ddint = 2.7 v, t a = 25 c, f ref = 16 mhz, unless otherwise noted.) characteristic symbol min typ max unit sensitivity for 1% packet error rate (per) (-40 to +85 c) sens per --92-dbm sensitivity for 1% packet error rate (per) (+25 c) - -92 -87 dbm saturation (maximu m input level) sens max -10-dbm channel rejection for 1% per (desired signal -82 dbm) +5 mhz (adjacent channel) -5 mhz (adjacent channel) +10 mhz (alternate channel) -10 mhz (alternate channel) >= 15 mhz - - - - - 31 30 43 41 53 - - - - - db db db db db frequency error tolerance - - 200 khz symbol rate error tolerance - - 80 ppm
mc13202/203 technical data, rev. 0.0 10 freescale semiconductor figure 6. rf parametric evaluation circuit table 5. transmitter ac electrical characteristics (v batt , v ddint = 2.7 v, t a = 25 c, f ref = 16 mhz, unless otherwise noted.) characteristic symbol min typ max unit power spectral density (-40 to +85 c) absolute limit - -47 - dbm power spectral density (-40 to +85 c) relative limit - 47 - nominal output power 1 1 spi register 12 programmed to 0x00bc which sets output power to nominal (-1 dbm typical). p out -4 -1 2 dbm maximum output power 2 2 spi register 12 programmed to 0x00fc which sets output power to maximum. 4dbm error vector magnitude evm - 20 35 % output power control range - 30 - db over the air data rate - 250 - kbps 2nd harmonic - tbd - dbc 3rd harmonic - tbd - dbc l2 6.8nh 5 1 6 2 3 4 z1 ldb212g4005c-001 l3 3. 9 n h c1 1.0pf r1 0r r2 0r not mount ed 1 2 5 3 4 j1 s ma_ e d ge _ r ec e p t a c c2 10 p f an t1 f_antenna pao_m 6 pao_p 5 rfin_p 2 rfin_m 1 ct_bias 3 u5 mc 1 32 0 x l1 1.8nh l4 1.8nh
mc13202/203 technical data, rev. 0.0 freescale semiconductor 11 6 functional description 6.1 mc13202/MC13203 operational modes the mc13202/MC13203 has a number of operational m odes that allow for low-current operation. transition from the off to idle mode occurs when rst is negated. once in idle, the spi is active and is used to control the ic. transition to hibernate and doze modes is enab led via the spi. these modes are summarized, along with the transition times, in table 6 . current drain in the va rious modes is listed in table 3 , dc electrical characteristics. 6.2 serial peripheral interface (spi) the host microcontroller directs the mc13202/MC13203, checks its status, and reads/writes data to the device through the 4-wire spi port. the transceiver operates as a spi slave device only. a transaction between the host and the mc13202/MC13203 occurs as mu ltiple 8-bit bursts on the spi. the spi signals are: 1. chip enable (ce ) - a transaction on the spi port is framed by the active low ce input signal. a transaction is a minimum of 3 spi bursts a nd can extend to a greater number of bursts. 2. spi clock (spiclk) - the hos t drives the spiclk input to the mc13202/MC13203. data is clocked into the master or slave on the leading (rising) edge of th e return-to-zero spiclk and data out changes state on the traili ng (falling) edge of spiclk. note for freescale microcontrollers, the spi clock format is the clock phase control bit cpha = 0 and the clock polarity control bit cpol = 0. 3. master out/slave in (mosi) - incoming data from the host is presented on the mosi input. 4. master in/slave out (miso) - the mc13202/MC13203 presents data to the master on the miso output. table 6. mc13202/MC13203 mode definitions and transition times mode definition transition time to or from idle off all ic functions off, leakage only. rst asserted. digital outputs are tri-stated including irq 10 - 25 ms to idle hibernate crystal reference oscillator off. (spi not functional.) ic responds to attn . data is retained. 7 - 20 ms to idle doze crystal reference oscillator on but clko out put available only if register 7, bit 9 = 1 for frequencies of 1 mhz or less. (spi not functional.) responds to attn and can be programmed to enter idle mode through an internal timer comparator. (300 + 1/clko) s to idle idle crystal reference oscillator on with clko output available. spi active. receive crystal reference oscillator on. receiver on. 144 s from idle transmit crystal reference oscillator on. transmitter on. 144 s from idle
mc13202/203 technical data, rev. 0.0 12 freescale semiconductor a typical interconnection to a microcontroller is shown in figure 7 . figure 7. spi interface although the spi port is fully static, in ternal memory, timer and interrupt ar biters require an internal clock (clk core ), derived from the crystal refere nce oscillator, to communicate from the spi registers to internal registers and memory. 6.2.1 spi burst operation the spi port of an mcu transfers data in bursts of 8 bi ts with most significant bit (msb) first. the master (mcu) can send a byte to the slave (transceiver) on the mosi line and the slave can send a byte to the master on the miso line. although an mc13202/MC13203 transa ction is three or more spi bursts long, the timing of a single spi burst is shown in figure 8 . figure 8. spi single burst timing diagram shift register baud rate generator shift register chip enable (ce) rxd miso txd mosi sclk spiclk mcu mc13202/203 ce 1 2345 678 ce spiclk t1 t2 t4 t0 spi burst valid t5 t6 t3 valid t7 mi so mosi valid
mc13202/203 technical data, rev. 0.0 freescale semiconductor 13 6.2.2 spi transaction operation although the spi port of an mcu transfers data in bursts of 8 bits, the mc13202/MC13203 requires that a complete spi transaction be framed by ce , and there will be th ree (3) or more bursts per transaction. the assertion of ce to low signals the start of a tr ansaction. the first spi burst is a write of an 8-bit header to the transceiver (mosi is valid) th at defines a 6-bit address of the internal resource being accessed and identifies the access as being a read or write operation. in this context, a write is data written to the mc13202/MC13203 and a read is da ta written to the spi master. the fo llowing spi bursts will be either the write data (mosi is valid) to the transceiver or read data from the transceiver (miso is valid). although the spi bus is capable of sending data si multaneously between master and slave, the mc13202/MC13203 never uses this mode. the number of da ta bytes (payload) will be a minimum of 2 bytes and can extend to a larger number depending on the type of access. the number of payload bytes sent will always be an even integer. after the final spi burst, ce is negated to high to signal the end of the transaction. an example spi read transaction wi th a 2-byte payload is shown in figure 9 . figure 9. spi read transaction diagram table 7. spi timing specifications symbol parameter min typ max unit t0 spiclk period 125 ns t1 pulse width, spiclk low 62.5 ns t2 pulse width, spiclk high 62.5 ns t3 delay time, miso data valid from falling spiclk 15 ns t4 setup time, c e low to rising spiclk 15 ns t5 delay time, miso valid from ce low 15 ns t6 setup time, mosi valid to rising spiclk 15 ns t7 hold time, mosi vali d from rising spiclk 15 ns ce spiclk miso mosi valid valid valid clock burst header read data
mc13202/203 technical data, rev. 0.0 14 freescale semiconductor 7 pin connections table 8. pin function description pin # pin name type description functionality 1 rfin_m rf input rf input/output negative. when used with internal t/r switch, this is a bi-directional rf port for the internal lna and pa 2 rfin_p rf input rf input/output positive. when used with internal t/r switch, this is a bi-directional rf port for the internal lna and pa 3 ct_bias control voltage bias voltage/control signal for external rf components when used with internal t/r switch, provides rx ground reference and tx vdda reference for use with external balun. can also be used as a control signal for external lna, pa, or t/r switch. 4 nc tie to ground. 5 pao_p rf output /dc input rf power amplifier output positive. open drain. connect to vdda through a bias network when used with an external balun. not used when internal t/r switch is used. 6 pao_m rf output/dc input rf power amplifier output negative. open drain. connect to vdda through a bias network when used with an external balun. not used when internal t/r switch is used. 7 sm input test mode pin. must be grounded for normal operation. 8 gpio4 digital input/ output general purpose input/output 4. 9 gpio3 digital input/ output general purpose input/output 3. 10 gpio2 digital input/ output general purpose input/output 2. when gpio_alt_en, register 9, bit 7 = 1, gpio2 functions as a ?crc valid? indicator. 11 gpio1 digital input/ output general purpose input/output 1. when gpio_alt_en, register 9, bit 7 = 1, gpio1 functions as an ?out of idle? indicator. 12 rst digital input active low reset. while held low, the ic is in off mode and all internal information is lost from ram and spi registers. when high, ic goes to idle mode, with spi in default state.
mc13202/203 technical data, rev. 0.0 freescale semiconductor 15 13 rxtxen digital input active high. low to high transition initiates rx or tx sequence depending on spi setting. should be taken high after spi programming to start rx or tx sequence and should be held high through the sequence. after sequence is complete, return rxtxen to low. when held low, forces idle mode. 14 attn digital input active low attention. transitions ic from either hibernate or doze modes to idle. 15 clko digital output clock output to host mcu. programmable frequencies of: 16 mhz, 8 mhz, 4 mhz, 2 mhz, 1 mhz, 62.5 khz, 32.786+ khz (default), and 16.393+ khz. 16 spiclk digital clock input external clock input for the spi interface. 17 mosi digital input master out/slave in. dedicated spi data input. 18 miso digital output master in/slave out. dedicated spi data output. 19 ce digital input active low chip enable. enables spi transfers. 20 irq digital output active low interrupt request. open drain device. programmable 40 k ? internal pull-up. interrupt can be serviced every 6 s with <20 pf load. optional external pull-up must be >4 k ? . 21 vddd power output digital regulated supply bypass. decouple to ground. 22 vddint power input digital interface supply & digital regulator input. connect to battery. 2.0 to 3.4 v. decouple to ground. 23 gpio5 digital input/output general purpose input/output 5. 24 gpio6 digital input/output general purpose input/output 6. 25 gpio7 digital input/output general purpose input/output 7. 26 xtal1 input crystal reference oscillator input. connect to 16 mhz crystal and load capacitor. table 8. pin function description (continued) pin # pin name type description functionality
mc13202/203 technical data, rev. 0.0 16 freescale semiconductor 27 xtal2 input/output crystal reference oscillator output note: do not load this pin by using it as a 16 mhz source. measure 16 mhz output at pin 15, clko, programmed for 16 mhz. see the mc13202/MC13203 reference manual for details. connect to 16 mhz crystal and load capacitor. 28 vddlo2 power input lo2 vdd supply. connect to vdda externally. 29 vddlo1 power input lo1 vdd supply. connect to vdda externally. 30 vddvco power output vco regulated supply bypass. decouple to ground. 31 vbatt power input analog voltage regulators input. connect to battery. decouple to ground. 32 vdda power output analog regulated supply output. connect to directly vddlo1 and vddlo2 externally and to pao through a bias network. note : do not use this pin to supply circuitry external to the chip. decouple to ground. ep ground external paddle / flag ground. connect to ground. table 8. pin function description (continued) pin # pin name type description functionality
mc13202/203 technical data, rev. 0.0 freescale semiconductor 17 figure 10. pin connections (top view) 1 2 3 gpio3 gpio2 gpio1 rst rxtxen attn clko spiclk 4 5 6 7 8 ct_bias rfin_p nc pao_p pao_m sm gpio4 rfin_m vddint gpio5 vddd irq ce miso mosi gpio6 12 13 14 15 16 11 10 9 24 23 22 21 20 19 18 17 vdda vbatt vddvco vddlo1 vddlo2 xtal2 xtal1 gpio7 ep 29 28 27 26 25 30 31 32 mc13202/ MC13203
mc13202/203 technical data, rev. 0.0 18 freescale semiconductor 8 crystal oscillator reference frequency 8.1 crystal oscillator design considerations the ieee 802.15.4 standard requires that severa l frequency tolerances be kept within 40 ppm accuracy. this means that a total offset up to 80 ppm between transmitter and recei ver will still result in acceptable performance. the mc132202/203mc132202/ 203 transceiver provides onboard crystal trim capacitors to assist in meeting this performance. the primary determining factor in me eting this specification is the to lerance of the crystal oscillator reference frequency. a number of fact ors can contribute to this toleran ce and a crystal specification will quantify each of them: 1. the initial (or make) tolerance of the crystal resonant frequency itself. 2. the variation of the crystal res onant frequency with temperature. 3. the variation of the crystal resonant frequency with time , also commonly known as aging. 4. the variation of the crystal re sonant frequency with load cap acitance, also commonly known as pulling. this is affected by: a) the external load capacitor values - init ial tolerance and variation with temperature. b) the internal trim capacitor values - initial tolerance and variation with temperature. c) stray capacitance on the crystal pin nodes - incl uding stray on-chip capacitance, stray package capacitance and stray board capacitance; and its initial tolerance and variation with temperature. 5. whether or not a frequency trim st ep will be performed in production freescale requires that a 16 mhz crystal with a <9 pf load capacitance is used. the mc13202/203 does not contain a reference divider, so 16 mhz is the only frequency that can be used. a crystal requiring higher load capacitance is prohibited because a highe r load on the amplifier circuit may compromise its performance. the crystal manuf acturer defines the load capacitance as that total external capacitance seen across the two terminals of the crystal. the osci llator amplifier configur ation used in the mc13202/203 requires two balanced load capacitors from each terminal of the crysta l to ground. as such, the capacitors are seen to be in series by the crystal, so each must be <18 pf for proper loading. in the figure 11 crystal reference schematic, the external lo ad capacitors are shown as 6.8 pf each, used in conjunction with a crystal that requires an 8 pf load capacitance. the default internal trim capacitor value (2.4 pf) and stray capacitance total value (6.8 pf ) sum up to 9.2 pf giving a total of 16 pf. the value for the stray capacitance was determin ed empirically assuming the default internal trim capacitor value and for a specific board layout. a differen t board layout may require a differen t external load capacitor value. the on-chip trim capability may be us ed to determine the closest standard value by adjusting the trim value via the spi and observing the frequency at clko. each internal trim load capacitor has a trim range of approximately 5 pf in 20 ff steps. initial tolerance for the internal trim capacitance is approximately 15%. since the mc13202/203 contains an on-chip reference frequency trim capabili ty, it is possible to trim out virtually all of the initial tole rance factors and put th e frequency within 0.12 ppm on a board-by-board
mc13202/203 technical data, rev. 0.0 freescale semiconductor 19 basis. individual trimming of each board in a production environment allows use of the lowest cost crystal, but requires that each board go through a trim ming procedure. this st ep can be avoided by using/specifying a crystal with a tighter stability tolerance, but the crysta l will be slightly higher in cost. a tolerance analysis budget may be created using all the previously stated factors. it is an engineering judgment whether the worst case tolerance will assume that all factors will vary in the same direction or if the various factors can be statistically rationalized using rss (root-sum-squa re) analysis. the aging factor is usually specified in pp m/year and the product designer can dete rmine how many years are to be assumed for the product life time. taking all of the fa ctors into account, the pr oduct designer can determine the needed specifications for the crystal and external load capacitors to meet the ieee 802.15.4 specification. figure 11. mc13202/203 modem crystal circuit 8.2 suggested crystals three suggested crystal types are shown in table 9 , table 10 , and table 11 . these variations are given because the crystals have different trade-offs between cost and usage. table 9. daishinku kds - dsx321g zd00882 crystal specifications 1,2 1 with this crystal oscillator frequency requires trimming in production. 2 this crystal not recommended for applications that employ doze mode over t he entire temperature range. parameter value unit condition type dsx321g surface mount frequency 16 mhz frequency tolerance 20 ppm at 25 c 3 c equivalent series resistance 100 ? max temperature drift 20 ppm -10 c to +60 c load capacitance 8.0 pf drive level 10 w 2 w shunt capacitance 2 pf max mode of oscillation fundamental y1 16mhz c10 6.8pf c11 6.8pf y1 = daishinku kds - dsx321g zd00882 xta l 1 26 xta l 2 27 u6 mc1320x
mc13202/203 technical data, rev. 0.0 20 freescale semiconductor table 10. toyocom tsx-10a 16mhz tn4-26139 crystal specifications 1,2 1 with this crystal oscillator frequency trimming is not required in production. 2 this crystal not recommended for applications that employ doze mode over t he entire temperature range. parameter value unit condition type tsx-10a surface mount frequency 16 mhz frequency tolerance 10 ppm at 25 c 3 c equivalent series resistance 40 ? max temperature drift 16 ppm -40 c to +85 c load capacitance 9 pf drive level 100 wmax shunt capacitance 1.2 pf typical mode of oscillation fundamental table 11. ndk exs00a-03311 crystal specifications 1,2 1 with this crystal oscillator frequency trimming is not required in production. 2 this crystal recommended for applications that employ doze mode. parameter value unit condition type nx3225 surface mount frequency 16 mhz frequency tolerance 10 ppm at 25 c 3 c equivalent series resistance 80 ? max (42 typ) temperature drift 15 ppm -40 c to +85 c load capacitance 7.2 pf drive level 100 wmax shunt capacitance 0.8 pf typical mode of oscillation fundamental
mc13202/203 technical data, rev. 0.0 freescale semiconductor 21 9 transceiver rf configurations and external connections the mc13202/203 radio has features that allow for a flexible as well as low cost rf interface: ? programmable output power - 0 dbm nominal out put power, programmable from -27 dbm to +4 dbm typical. ? <-94 dbm (typical) receive sens itivity - at 1% per, 20-byt e packet (well above ieee 802.15.4 specification of -85 dbm). ? optional integrated transmit/rece ive (t/r) switch for low cost operation - with internal pas and lna, the internal t/r switch al lows a minimal part count radio interface using only a single balun to interface to a single-ended antenna. ? maximum flexibility - there are full differential rf i/o pins for use with the internal t/r switch. optionally, these pins become the rf_in signals and a separate set of full differential pa outputs are also provided. separa te inputs and outputs allow for a vari ety of rf confi gurations including external lna and pa for increased range. ? ct_bias output - the ct_bias si gnal provides a switched bias reference for use with the internal t/r switch, and alternatively ca n be programmed as an antenna switch signal for use with an external antenna switch. ? onboard trim capability for 16 mhz crystal referenc e oscillator - the ieee 802.15.4 standard puts a +/- 40 ppm requirement on the carrier freque ncy. the onboard trim capability of the modem crystal oscillator eliminates need for external variable capacitors and allows for automated production frequency calibration. al so tighter tolerance can produc e greater receive sensitivity. 9.1 rf interface pins figure 12 shows the rf interface pins and the associated analog blocks. notice that separate pa blocks are associated with rfin_x and pao_x signal pairs. th e rf interface allows both single port differential operation and dual port differential operation.
mc13202/203 technical data, rev. 0.0 22 freescale semiconductor figure 12. rf interface pins 9.1.1 single port operation the integrated rf switch allows us ers to operate in a single port conf iguration. in single port mode, an internal rx switch and separate pa are used a nd pins rfin_p (pao_p) a nd rfin_m (pao_m) become bidirectional and connect both for tx and rx. when receiving, the rx switch is enabled to the internal lna and the tx pa is disabled. wh en transmitting, the rx switch is di sabled (isolating the lna) and a tx pa is enabled. the optional ct_bias pin provides a reference or bias volta ge which is at vdda for transmit and is at gr ound for receive. this signal can be used to provide the proper bias voltage to a balun that converts a single-ended antenna to the diff erential interface required by the transceiver. figure 13. single port rf operation with a balun figure 13 shows a single port example with a balun. the ct_bias is connected to the balun center-tap providing the proper dc bias voltage to the balun depending on rx or tx. rx switch pa2 enable ct_bias control pa2 pa1 from tx psm rx enable lna rx signal rfin_p (pao_p) rfin_m (pao_m) ct_bias pao_p pao_m 2 1 3 5 6 mc13202/203 pa1 enable ct_bias generator balun bypass rfin_p (pao_p) rfin_m (pao_m) ct_bias pao_p pao_m mc13202/03 l1
mc13202/203 technical data, rev. 0.0 freescale semiconductor 23 9.1.2 dual port operation a second set of pins designated pao_p and pao_n allow operation in a dual port configuration. there are separate paths for transmit a nd receive with the optional ct_bias pin providing a signal that indicates if the radio is in tx or rx mode which then can be used to driv e an external low noise amplifier, power amplifier, or antenna switch. in dual port operation, the rfin_p and rfin_n are inputs only, the internal rx switch to the lna is enabled to receive, and the associated tx pa st ays disabled. pins pao_p and pao_n become the differential output pins and the associ ated tx pa is enabled for transmit. figure 14 shows two dual port configurations . first is a single antenna confi guration with an external low noise amplifier (lna) for greater range. an external antenna switch is used to multiplex the antenna between receive and transmit. an lna is in the receive path to add gain for greater receive sensitivity. two external baluns are required to convert the si ngle-ended antenna switch si gnals to the differential signals required by the radio. separate rfin and pao signals are provided for connect ion with the baluns, and the ct_bias signal is pr ogrammed to provide the exte rnal switch control. the polarity of the external switch control is selectable. figure 14 also shows a dual antenna confi guration where there is a rx an tenna and a tx antenna. for the receive side, the rx antenna is ac-c oupled to the differential rfin i nputs and these capacitors along with inductor l1 form a matching network. inductors l2 and l3 are ac-coupled to ground to fo rm a frequency trap. for the transmit side, the tx antenna is connected to the differential pao out puts, and inductors l4 and l5 provide dc-biasing to vdda but are ac-isolated. ct_b ias is not required or used.
mc13202/203 technical data, rev. 0.0 24 freescale semiconductor figure 14. dual port rf configuration examples balun bypass rfin_p (pao_p) rfin_m (pao_m) ct_bias (ant sw ctl) pao_p pao_m mc13202/03 lna ant sw balun vdd vdda bypass l1 using external antenna switch with lna rfin_p (pao_p) rfin_m (pao_m) ct_bias pao_p pao_m mc13202/03 vdda tx antenna bypass bypass l1 l2 l3 l4 l5 rx antenna using dual antenna
mc13202/203 technical data, rev. 0.0 freescale semiconductor 25 9.2 controlling rf modes of operation use of the rf interface pins and rf modes of ope ration are controlled through several bits of modem control_b register 07. figure 15 shows the model for register 07 wi th the rf interface control bits highlighted. figure 15. control_b register 07 model the rf interface control bits include: ? rf_switch_mode (bit 12) - this bit selects dual port mode vers us single port mode: ? the default condition (bit 12 = 0) is dual po rt mode where the rf inputs are rfin_m and rfin_p and the rf outputs are pao_m and pao_p, and operation is as described in section 9.1.2, ?dual port operation? . the use of ct_bias pin in du al port mode is controlled by bit 13 and bit 12. ? when bit = 1, the single port mode is se lected where rfin_m (pao_m) and rfin_p (pao_p) become bidirectional pins and operation is as described in section 9.1.1, ?single port operation? . the use of ct_bias pin in dual port mode in controlled by bit 13 and bit 12. ? ct_bias_en (bit 14) - this bit is the enable for the ct_bia s output. when bit 14 = 0 (default), the ct_bias is disabled and stays in a hi-z or tri-stated condition. when bit 14 = 1, the ct_bias output is active and its state is controlled by th e selected mode (bit 12) , ct_bias_inv, and operation of the radio. ? ct_bias_inv (bit 13) - this bit only affects the state of ct_bias when dual port mode is selected and ct_bias is active. the ct_bia s changes state in dual port m ode based on the tx or rx state of the radio. the ct_bias_inv bit caus es the sense of the active stat e to change or invert based on bit 13?s setting. in this manner, the user can sel ect the ct_bias as a control signal for external components and make the control si gnal active high or active low. register 07 0x07 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmr_load ct_bias_en ct_bias_inv rf_switch_mode miso_hiz_en clko_doze_en tx_done_mask rx_done_mask use_strm_mode hib_en doze_en type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0x0c00
mc13202/203 technical data, rev. 0.0 26 freescale semiconductor table 12 summarizes the operation of th e rf interface control bits. 9.3 rf control output ct_bias ct_bias is a useful signal for interf ace with external rf components. it must be enabled via the ct_bias_en control bit, and then its state is determined first by th e selected rf mode and then by the active state of the radio, i.e., whether a tx or rx operation is active: ? single port operation - in this mode, the ct_bia s can be used to establish the proper dc bias voltage to a balun depending on the rx state versus tx state as described in section 9.1.1, ?single port operation? . note that in single port operation, the ct_bias_inv has no effect and ct_bias is at vdda for tx and is at ground for rx. ? dual port operation - in this m ode, the ct_bias can be used as a control signal to enable a lna or pa or to determine the direction of an antenna switch as described in section 9.1.2, ?dual port operation? . in dual port operation, ct-bias_inv is used to control the sense of the output control, i.e., ct_bias can be active high or activ e low for tx and vice-versa for rx. table 13 defines the ct_bias output state depending on c ontrol bits and operation mode of the modem. note that the output state is also defined in idle, hibernate, and do ze state as well as rx and tx operation. table 12. rf interface control bits bit designation de fault operation 14 ct_bias_en 0 1 = ct_bias enabled. output state is defined by table 13 . 0 = ct_bias disabled. output state is tri-stated. 13 ct_bias_inv 0 the output state of ct_bias under varying conditions is defined in ta b l e 1 3 . this bit only has effect for dual port operation. 1 = ct_bias inverted. 0 = ct_bias not inverted 12 rf_switch_mode 0 1= single port mode selected where rf switch is active and rfin_m and rfin_p and bidirectional signals. 0 = dual port mode selected where rfin_m and rfin_p are inputs only and pao_p and pao_n are separate outputs. (this is default operation). table 13. ct_bias output vs. register settings mode ct_bias_en rf_switch_mode ct_bias_inv ct_bias rx 1 1 0 0 rx 1 1 1 0 rx 1 0 0 0 rx 0 x x hi-z rx 1 1 0 1 tx 1 1 0 1 tx 1 1 1 1 tx 1 0 0 1
mc13202/203 technical data, rev. 0.0 freescale semiconductor 27 9.4 rf single port appli cation with an f antenna figure 16 shows a typical single port rf a pplication in which part count is minimized and a printed copper f antenna is used for low cost. only the rfin port of the mc13202/203 is required because the differential port is bi-directional and uses the on-chip t/r switch. matching to near 50 ohms is accomplished with l1, l2, l3, and the traces on the pcb. a balun transforms the differential signal to single-ended to interface with the f antenna. the proper dc bias to the rfin_x (pao_x) pins is provided through the balun. th e ct_bias pin provides the proper bias voltage point to th e balun depending on operation, that is , ct_bias is at vdda voltage for transmit and is at ground for receive. ct_bias is switched between these two voltages based on the operation. capacitor c2 provides some high frequency bypass to the dc bias point. the l3/c1 network provides a simple bandpass filter to limit out-of-band harm onics from the transmitter. figure 16. rf single port application with an f-antenna tx 1 0 1 0 tx 0 x x hi-z idle 1 x x 0 idle 0 x x hi-z doze 1 x x 0 doze 0 x x hi-z hibernate 1 x x 0 (low-z) hibernate 0 x x hi-z offxxxunknown table 13. ct_bias output vs. register settings (continued) mode ct_bias_en rf_switch_mode ct_bias_inv ct_bias l2 6.8nh 5 1 6 2 3 4 z1 ldb212g4005c-001 l3 3. 9 n h c1 1.0pf r1 0r r2 0r not mount ed 1 2 5 3 4 j1 s ma_ e d ge _ r ec e p t a c c2 10pf an t1 f_antenna pao_m 6 pao_p 5 rfin_p 2 rfin_m 1 ct_bias 3 u5 mc 1 32 0 x l1 1.8nh l4 1.8nh
mc13202/203 technical data, rev. 0.0 28 freescale semiconductor 10 packaging information figure 17. outline dimensions for qfn-32, 5x5 mm (case 1311-03, issue e) n exposed die attach pad 2.95 25 8 1 32 3.25 32x 0.18 0.30 24 17 16 9 0.5 m 0.1 c m 0.05 c a b 32x 0.5 0.3 c 0.1 a b c 0.1 a b view m-m 0.25 28x detail m pin 1 index 2.95 3.25 pin 1 index area 5 b c 0.1 2x 2x c 0.1 a 5 g m m 1.0 1.00 0.05 c 0.1 c 0.05 c seating plane 5 detail g view rotated 90 clockwise (0.5) (0.25) 0.8 0.75 0.00 (1.73) (0.25) 0.065 32x 0.015 (45 ) 5 4 preferred corner configuration detail n 0.60 0.24 0.60 0.24 4 detail n corner configuration option detail t detail m backside pin 1 index option detail t backside pin 1 index option (90 ) 5 2x 2x 0.39 0.31 0.1 0.0 detail m backside pin 1 index option 1.6 0.475 0.425 1.5 backside pin 1 index 0.25 0.15 r detail s detail m preferred backside pin 1 index 0.217 0.137 (0.25) 0.217 0.137 (0.1) detail s preferred backside pin 1 index notes: 1. all dimensions are in millimeters. 2. dimensioning and tolerancing per asme y14.5m, 1994. 3. the complete jedec designator for this package is: hf-pqfp-n. 4. corner chamfer may not be present. dimensions of optional features are for reference only. 5. coplanarity applies to leads, corner leads, and die attach pad. 6. for anvil singulated qfn packages, maximum draft angle is 12.
notes mc13202/203 technical data, rev. 0.0 freescale semiconductor
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